Abstract: This research presents an innovative FPGA implementation of a $128 \times 128$ convolution systolic array architecture, optimized for image processing applications. The core of this design ...
Abstract: A hybrid 1T-1C HfZrOx(HZO)-DRAM/FRAM (D-FRAM) enabling non-volatile memory (NVM) and DRAM modes at 130 nm node are experimentally demonstrated. Excellent data retention characteristics at ...
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